The present disclosure relates generally to chip manufacturing, and more particularly to methods, systems and computer program products for performing test and calibration of integrated sensors on a processor chip.
The rapid densification of very-large-scale integration (VLSI) devices, incorporating complex functions operating at extreme circuit performance, has driven the designs towards integrating many diverse functional macros or cores within these large chips. These macros range from autonomous processor cores with large cache arrays occupying relatively large portions of the chip's real estate, to a multitude of small arrays used as register stacks, trace arrays, content addressable memories, phase locked loops (PLLs), and many other special purpose logic functions. In conjunction with these higher integration densities and larger devices, current system architecture is shifting, in many applications, toward massively parallel processing utilizing multiple copies of these integrated cores. The number of processing cores can range from dual-cores to hundreds of cores per chip in the near future and to thousands of core arrays at system level. The independent logic units may include register stacks, trace arrays, content addressable memories, PLLs, as well as various integrated sensors (or on-chip sensors) such as Critical Path Monitors (CPM) and Digital Temperature Sensors (DTS) used for real time monitoring and environmental optimization.
The problem addressed by this disclosure is encountered while utilizing on-chip sensors to optimize the power and performance of the device. Specifically, the problem is to accurately and rapidly test and calibrate the various sensors during test.
Therefore, heretofore unaddressed needs still exist in the art to address the aforementioned deficiencies and inadequacies.